1. Field of the Invention
This invention relates generally to the field of data synchronizers. More particularly, the present invention relates to phase and frequency detectors in data synchronizers that can function as phase detectors without the need for a delay lock loop (DLL).
2. Description of the Related Art
Data communication and synchronization applications typically use a clock signal to synchronize and regulate the processing of data signal. For data processing, for example, the clock signals typically extracted from an incoming digital (e.g., binary) data signal in a digital signal format such as non-return-to-zero (NRZ) format. These applications generally use a phase-locked loop (PLL), often called data synchronizer or frequency synthesizer, to synchronize a clock signal with a digital data signal.
In data transmission, user data is often preceded by a preamble such as a sync field that contains a regular pattern of digital data. In data synchronizers, a phase and frequency detector may be used to lock the phase and frequency of the clock signal to that of the sync data whenever a sync field is encountered. In this manner, the clock in the data synchronizer is kept synchronized to the phase and frequency of the sync data.
After locking phase and frequency of the clock to the sync data, the data synthesizer receives data in the data field. In contrast to the data, the data in the data field is a random pattern of 0's and 1's. When such random data pattern is encountered, the data synchronizer needs to maintain a phase lock to the data while detecting the data. For such purposes, the data synchronizer uses a phase detector to maintain the phase lock.
Conventional data synchronizers have two main modes of operation: data/clock recovery and idle. During an idle mode, a data synchronizer locks to both the frequency and phase of a reference clock. On the other hand, during data recovery, the data synchronizer locks to only the phase of the incoming data since the frequency of the data changes depending on the data pattern. For example, a data pattern "001100110011" has a frequency twice that of a data pattern "000011110000." However, because the data rate is the same for both patterns, the data synchronizer must recover the same clock for both patterns.
Traditionally, a delay lock loop (DLL), which is well known in the art, is used in conjunction with a phase and frequency detector to perform the two modes of operation. When used alone, the phase and frequency detector will perform both phase and frequency detection at the same time. The DLL is used to produce a data stream that is exactly 50% delayed. The non-delayed data is used to enable the phase and frequency detector. The delayed data is sent to the phase and frequency detector as data. Hence, the phase and frequency detector is enabled only for error correction when the data makes a transition from a "0" to "1". In this manner, the DLL allows the phase and frequency detector to make only phase corrections and not frequency corrections.
FIG. 1 shows a schematic circuit diagram of a conventional phase and frequency detector 100 used with a data synchronizer. The phase and frequency detector 100 includes a pair of D flip-flops 102 and 104, an AND gate 106, and an OR gate 108. The D flip-flops 102 and 104 are configured to receive a reference clock REFCLK which is the 50% delayed DATA and a voltage controlled oscillator (VCO) clock VCOCLK from a VCO (not shown), respectively. In addition, the "D" input ports of the flip-flops 102 and 104 are coupled to a high voltage rail vdd. The D flip-flops 102 and 104 generate output signals UP and DOWN, respectively. The UP and DOWN signals are correction signals that are provided to a charge pump (not shown) to speed up and slow down, respectively, the VCO that generates the VCOCLK.
As is well known in the art, each of the D flip-flops 102 and 104 outputs the states that is present on the "D" input as UP or DOWN signal whenever the clock signal goes high at the other input port (i.e., REFCLK and VCOCLK). The AND gate 106 is coupled to receive the outputs of the D flip-flops 102 and 104 as inputs and generates an output signal, which is provided to the OR gate 108 as an input. The OR gate 108 also configured to receive DATA during the phase only mode only. During phase and frequency lock mode, i.e., sync field, DATA is set to "1." In response to the input signals, the OR gate 108 generates a reset signal RESET that is used to reset the flip-flops 102 and 104. By either speeding up or slowing down the VCO via the charge pump using the UP and DOWN signals, the phase and frequency detector 100 locks the phase and frequency of the VCOCLK to those of the reference clock REFCLK.
When the phase and frequency detector 100 is used to detect data, the D flip-flop 102 receives incoming data signal as REFCLK. FIG. 2 illustrates a timing diagram 200 of the phase and freguency detector 100 when synchronizing REFCLK to DATA preamble signal. At the rising edge of the reference clock signal REFCLK at time T3, the signal DOWN is activated while UP signal remains inactive. Then, for a full cycle from time T3 time T5, the DOWN signal is provided to the charge pump to slow down the VCO because the REKCLK is deemed to be faster than the data. At the rising edge of next REFCLK pulse (i.e., time T5), the phase and frequency detector 100 detects the transition of data signal to high. The signals UP and DOWN are both high at this point so that no correction is needed. In response to the simultaneous activation of UP and DOWN signals, the AND gate 106 generates a RESET signal, which is provided for resetting the flip-flops 102 and 104. As used herein, the DOWN and UP signals are correction signals and the net result of DOWN and UP signals is shown in FIG. 2 as waveform CORRECTION.
As can be seen from the timing diagram 200, however, the phase and frequency detector 100 over corrects by a full clock cycle when a data pattern of two clocks periods is received. For example, from T3 to T5 and again from T7 to T9, the phase and frequency detector 100 overcorrects as indicated by the CORRECTION signal. This is because the signal DOWN should not have been activated at the second rising edge of REFCLK signal (i.e., time T3) because the REFCLK phase is aligned properly in phase. On the following REFCLK cycle (i.e., at time T5), the phase and frequency detector then activities the UP signal which resets the phase and frequency detector 100. This same error occurs again at time T7.
The source of such over correction is that the phase and frequency detector 100 is comparing the incoming data's phase and frequency against the data synchronizer clock, which is typically a stream of pattern such as "010101010101." If the data pattern were in a form such as "001100110011," the phase and frequency detector would try to slow the data synchronizer clock down to match the frequency of the data. In practice, however, the data synchronizer clock typically need to be at higher frequency. Otherwise, the data will be recovered at the improper data rate. Clearly, the phase and frequency detector 100 will not recover data correctly without a gating signal. A DLL will provide the 50% delay DATA as a gating pulse.
The drawback of using the phase and frequency detector 100 to synchronize only phase of the VCOCLK to the data signal REFCLK is cost. In particular, using the phase and frequency detector 100 to track the phase of the data signal requires costly analog hardware such as a delay lock loop (DLL) with its own charge pump, loop filter, and a phase and frequency detector. Furthermore, such hardware arrangement typically requires substantially higher power that a complete digital solution for proper operation.
Thus, what is needed is a phase and frequency detector that can also be used for efficiently tracking phase of data signals without the high costs involved in conventional phase and frequency detectors.